The present invention relates to integrated circuits, and more particularly to nonvolatile integrated memories.
FIG. 1 shows a cross section of a stacked gate nonvolatile memory cell such as used in flash and non-flash electrically erasable programmable read only memories (EEPROM). Conductive floating gate 110, made of doped polysilicon, overlies monocrystalline silicon substrate 120. Silicon dioxide 130 insulates the floating gate from the substrate. N type source/drain regions 140 in substrate 120 are separated by
type channel region 150. Channel region 150 is directly below the floating gate. Dielectric 160 separates the floating gate from control gate 170 made of doped polysilicon.
The memory cell is read by applying a voltage between the regions 140, applying a voltage between one of the regions 140 and control gate 170, and detecting a current through the other one of the regions 140. The memory cell is written (programmed or erased) by modifying a charge on floating gate 110. Floating gate 110 is completely insulated on all sides. To modify the charge on the floating gate, electrons are transferred between the floating gate and substrate 150 through oxide 130. The electrons can be transferred by Fowler-Nordheim tunneling or hot electron injection. See “Nonvolatile Semiconductor Memory Technology” (1998) edited by W. D. Brown and J. E. Brewer, pages 10–25, incorporated herein by reference. The electron transfer requires a voltage to be established between the floating gate and a substrate region (the substrate region can be channel 150 or a source/drain region 140). This voltage is established by creating a voltage between the substrate region and the control gate. The control gate voltage is coupled to the floating gate. To reduce the voltage required to be created between the substrate region and the control gate, a high capacitive coupling is needed between the floating and control gates. A high specific capacitance (capacitance per unit area) can be obtained between the floating and control gates by reducing the thickness of dielectric layer 160. However, dielectric layer 160 functions as a barrier to a charge leakage from the floating gate to the control gate. Therefore, dielectric 160 has to be a high quality, thin, uniform dielectric in order to provide good data retention (low leakage) and ensure a predictable high capacitive coupling between the floating and control gates.
Dielectric 160 can be silicon dioxide as shown in FIG. 1. However, as the dimensions of the devices continues to shrink, the thickness of the SiO2 layer must also decrease to maintain the same capacitance between the floating gate and the control gate. Thicknesses of less than 2 nm are expected in the future. However, the occurrence of high tunneling current through such thin layers of SiO2 requires that alternative materials be considered. ONO (silicon dioxide, silicon nitride, silicon dioxide) has been used as dielectric layer 160. See U.S. Pat. No. 4,613,956 issued Sep. 23, 1986 to peterson et al. The nitride layer has a higher dielectric constant than silicon dioxide, thus increasing the capacitive coupling between the floating gate and the control gate. The higher capacitive coupling allows a thicker layer to be used to reduce leakage current without diminishing the capacitive coupling. Another option is a combination of silicon dioxide and oxynitride layers for dielectric layer 160. Thus, according to U.S. Pat. No. 6,274,902, a silicon dioxide layer is thermally grown on floating gate polysilicon, and an oxynitride layer is deposited by LPCVD (low pressure chemical vapor deposition) on the silicon dioxide.